According to Shannon's transmission model, data originating from a data source are transmitted by a transmitter via a transmission channel to a receiver and output from the latter to a data sink. During the transmission via a real transmission channel, the reception signal generally has linear distortions and an additional noise component. The noise component can be modelled by additive white Gaussian noise (AWGN). The task of the receiver is to reconstruct the bit sequence of the data source from the reception signal. In this case, a reception filter suppresses possible interference signals outside the transmission frequency band. Through suitable dimensioning of a matched filter, in particular, the reliability of the detection is thereby greatly increased. The timing of the transmission pulses is recovered by a synchronization device. In this case, the reception signal is sampled and fed to a threshold value decision unit, which outputs a detected bit sequence for further data processing. If additive noise severely interferes with the data transmission, a so-called matched filter (MF) is used within the receiver. This reception filter is specifically matched to the basic transmission pulse, so that a maximum signal-to-noise ratio (SNR) is achieved at the detection instants. The impulse response of the matched filter (MF) is usually set to be equal to the temporally mirrored basic transmission pulse or basic transmission pulse shifted by a bit duration. The matched filter is a digital reception filter within the receiver which is matched to a transmission filter within the transmitter in such a way that the amplitude of the received signal is maximal at the sampling instants. The matched filter can be of adaptive construction, so that it can be matched to the transmission channel, or an adaptive equalizer which compensates for the distortion of the transmission channel may be provided downstream or upstream of the matched filter. Frequency matched filter (FMF) is a term denoting a digital filter whose transfer function in the frequency domain is equal to the first derivative of the transfer function of an associated matched filter. For timing recovery, the receiver contains a synchronization device with a clock phase detector for the detection of the clock phase deviation between desired sampling instants and the sampling instants of a reception signal.
FIG. 1 shows a receiver according to the prior art. The receiver contains an analog/digital converter ADC for converting the analog reception signal into a digital reception signal, which is fed to a mixer. Connected downstream of the mixer is a digital resampling filter which outputs a digital output signal whose symbol rate is a factor r higher than the symbol rate of the digital reception signal. The digital output signal of the resampling filter is fed to the matched filter of the receiver, which outputs the filtered output signal with a decimated data symbol rate for further data processing. The output signal of the resampling filter is furthermore fed to a frequency matched filter which is associated with the matched filter and outputs a filtered output signal to a carrier frequency detector TFD. The filtered output signal of the matched filter MF is forwarded to a clock phase detector TPD, which is provided for clock phase detection of the digital reception signal. The clock phase detector TPD and the carrier frequency detector TFD are connected, on the output side, in each case to a digital loop filter and to an NCO which supplies a control signal. The clock phase detector TPD outputs a clock phase deviation signal TP to the associated digital loop filter and the NCO connected downstream supplies a digital control value for the driving of the resampling filter. The resampling filter carries out keying of the reception signal, band limiting simultaneously being effected. In this case, the control signal output by the NCO sets the sampling instant in a manner dependent on the filtered clock phase deviation signal.
The clock phase detector TPD according to the prior art is referred to as a Gardner clock phase detector after its developer F. M. Gardner. In the case of the receiver according to the prior art as illustrated in FIG. 1, the digital clock and carrier frequency recovery is effected without recourse being made to decisions in the process. This is also referred to as NDA (non decision aided) timing parameter estimation. In this case, sampling signal values are used for clock and carrier signal recovery which are taken downstream of a matched filter or an equalizer for clock and carrier recovery. Such receivers are described for example in Heinrich Meyr “Digital Communication Receivers” Wiley, N.Y., 1998.
The disadvantage of a receiver which contains a clock phase detector TPD according to the prior art consists in the fact that the conventional Gardner NDA clock phase detector has a considerable inherent noise. The output signal of the clock phase detector TPD has a high variance.
FIG. 2 shows a clock phase detector with Gardner architecture according to the prior art, as is contained in the receiver illustrated in FIG. 1. The clock phase detector TPD receives, from the matched filter MF, a filtered digital input signal which is fed to a delay circuit and a differentiator. The differentiator carries out differentiation of the received digital input signal with respect to time, and multiplies the differentiated signal by the time-delayed output signal of the matched filter MF.
FIG. 3 shows the signal amplitude of the output signal of the matched filter with respect to the clock phase deviation. At the clock phase deviation zero, the first derivative of the output signal of the matched filter or the input signal of the clock phase detector is indeterminate and may be either greater than or less than zero. In other words, at a clock phase deviation which fluctuates around the ideal value, the conventional clock phase detector outputs an output signal with a high variance. The output signal of the conventional clock phase detector thus has a considerable inherent noise. In order to suppress this inherent noise, it is necessary to provide a digital loop filter connected downstream, which is complex in terms of circuitry. As a result of such a loop filter of complex construction, however, the receiver becomes temporally sluggish and cannot follow variations in the digital input signal. Conversely, if a digital loop filter having relatively low complexity in terms of circuitry is used, the inherent noise of the clock phase detector according to the prior art leads to a relatively inaccurate control signal for the resampling filter, so that the bit error rate rises.